1. Field of the Invention
The present invention relates to an apparatus and method for detecting errors in received data and transferring only error-free data in data communications, and more particularly, to a cyclic redundancy check (CRC) verification apparatus and method having a constant delay, in which irrespective of the length of a received data frame, input and output processing delay of received data is made to be constant.
2. Description of the Related Art
In the Ethernet passive optical network (PON), for which standardization is in progress at present, an important condition that delay time of data transmission and reception processing should be constant should be satisfied. Meanwhile in the conventional Ethernet, data processing delay varies according to the length of a frame, because when CRC is performed in a receiving side, CRC should be verified for each variable-length frame.
In the prior art Ethernet data reception unit, the result of CRC verification is obtained at the end of a frame, and according to the CRC verification result, if there is a CRC error, the received frame should be discarded. In the prior art CRC verification method, a received data frame is buffered till the result of CRC verification comes out, and if the verification result comes out, this buffer is read and transferred to a next block. A part for reading and a part for writing in the buffer operate independently to each other. While a received data frame is being written in the buffer, if the CRC verification result comes out at the ending part of the frame as a normal one, a frame counter is increase by 1 and it is regarded that one frame is received.
If the CRC verification result comes out as an abnormal one, a write pointer is reset. Accordingly the part from which writing the received data frame begins is pointed again and it is the same state where the received data does not exist. Therefore, in this prior art method, a time taken for a received data frame to pass a CRC verification unit varies according to the length of the frame.
FIG. 1 is a timing diagram showing the change of frame processing time by prior art CRC verification method.
In FIG. 1, ta 110 denotes a delay time from the time when a received data frame is written in a buffer to the time the input of one frame is recognized, and the data frame stored in the buffer is read, and tb 120 denotes a delay time from a time when one data frame is read from the buffer to the time when another data frame is continuously read when storage of the data frame is recognized.
As shown in FIG. 1, though the short second frame arrives a predetermined time after the first frame arrives, when outputting frames after storing, the second frame is read immediately after the first frame is read and therefore according to the length of a received data frame, the time taken to pass the buffer varies. The reason is that while writing and reading are independently performed, a writing side finishes writing a frame and then, if the CRC result is normal, the writing side informs the reading side of the fact so that the reading side can read. Since reading the long first frame 130 begins after the frame is completely received and the result of CRC verification comes out, delay occurs as much as the length of the frame. If the short second frame 140 is input in the middle of reading the first frame 130, if the reading the first frame 130 is finished, the short second frame is already stored and the CRC result is already known, and accordingly, the second frame 140 is read immediately. Therefore, the delay time each frame takes varies.
The method described above causes no particular problem in the conventional Ethernet data reception unit, but in the Ethernet PON the delay time of a data frame in a reception unit should be constant in order to measure a round trip time (RTT) for each optical network unit (ONU). Accordingly, if the prior art method described above is used in the Ethernet PON, the delay time cannot be made to be constant.